1 of 6 092500 features all-silicon timing circuit five delayed clock phases per input precise tap-to-tap nominal delay tolerances of 0.75 and 1 ns input-to-tap 1 delay of 5 ns nominal delay tolerances of 1.5 ns leading and trailing edge precision preserves the input symmetry cmos design with ttl compatibility standard 8-pin dip and 150 mil 8-pin soic vapor phase, ir and wave solderable available in tape and reel pin assignment pin description tap 1-5 - tap output number v cc - +5v supply gnd - ground in - input description the ds1004 is a 5-tap all silicon delay line which can provide 2, 3, 4, or 5 ns tap-to-tap delays within a standard part family. the device is dallas semiconductor?s fastest 5-tap delay line. it is available in a standard 8-pin dip and 150 mil 8-pin mini-soic. the device features precise leading and trailing edge accuracies and has the inherent reliability of an all-silicon delay line solution. the ds1004 is specified for tap-to-tap tolerances as shown in table 1. each device has a minimum input-to-tap 1 delay of 5 ns. subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4, or 5 ns. see table 1 for details. input to tap tolerance over temperature and voltage is 1.5 ns in addition to the nominal delay tolerance. nominal tap-to-tap tolerances range from 0.75 ns to 1.0 ns. each output is capable of driving up to 10 ls loads. for customers needing non-standard delay values, the late package program (lpp) is available. customers may contact dallas semiconductor at (972) 371?4348 for further details. ds1004 5-tap high speed silicon delay line www.dalsemi.com in tap 2 tap 4 gnd v cc tap 1 tap 3 tap 5 1 2 3 4 6 5 8 7 ds1004m 8-pin dip (300-mil) see mech. drawings sectio n in tap 2 tap 4 gnd v cc tap 1 tap 3 tap 5 1 2 3 4 6 5 8 7 ds1004z 8-pin soic (150-mil) see mech. drawings sectio n
ds1004 2 of 6 part number tolerance table table 1 input-to-tap tolerance tap-to-tap tolerance part number nominal 1 over temp & voltage 2 nominal 1 over temp & voltage 2 ds1004m-2 1.5 ns 3.0 ns 0.75 ns 1.5 ns ds1004m-3 1.5 ns 3.0 ns 0.75 ns 1.5 ns ds1004m-4 1.5 ns 3.0 ns 1.0 ns 1.75 ns ds1004m-5 1.5 ns 3.0 ns 1.0 ns 1.75 ns ds1004z-2 1.5 ns 3.0 ns 0.75 ns 1.5 ns ds1004z-3 1.5 ns 3.0 ns 0.75 ns 1.5 ns DS1004Z-4 1.5 ns 3.0 ns 1.0 ns 1.75 ns ds1004z-5 1.5 ns 3.0 ns 1.0 ns 1.75 ns notes: 1. nominal conditions are +25 c and v cc = +5.0v 2. temperature and voltage variations cover the range from v cc =5.0v = 5% and temperature range from 0 c to +70 c. 3. delay accuracy for both leading and trailing edges. part number delay table table 2 nominal values (for reference only) part number input-to- tap1 input-to- tap2 input-to- tap3 input-to- tap4 input-to- tap5 ds1004m-2 5 ns 7 ns 9 ns 11 ns 13 ns ds1004m-3 5 ns 8 ns 11 ns 14 ns 17 ns ds1004m-4 5 ns 9 ns 13 ns 17 ns 21 ns ds1004m-5 5 ns 10 ns 15 ns 20 ns 25 ns ds1004z-2 5 ns 7 ns 9 ns 11 ns 13 ns ds1004z-3 5 ns 8 ns 11 ns 14 ns 17 ns DS1004Z-4 5 ns 9 ns 13 ns 17 ns 21 ns ds1004z-5 5 ns 10 ns 15 ns 20 ns 25 ns logic diagram
ds1004 3 of 6 ds1004 test circuit figure 1 test setup description figure 1 illustrates the hardware configuration used for measuring the timing parameters of the ds1004. the input waveform is produced by a precision pulse generator under software control. time delays are measured by a time interval counter (20 ps resolution) connected to the output. the ds1004 output taps are selected and connected to the interval counter by a vhf switch control unit. all measurements are fully automated with each instrument controlled by the computer over an ieee 488 bus.
ds1004 4 of 6 absolute maximum ratings* voltage on any pin relative to ground -1.0v to +7.0v operating temperature 0 c to 70 c storage temperature -55 c to +125 c soldering temperature see j-std-020a specification short circuit output current 50 ma for 1 second * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (0c to 70c; v cc = 5.0v 5%) parameter sym test condition min typ max units notes supply voltage v cc 4.75 5.00 5.25 v 1 active current i cc v cc =5.25v period=1 s 35 75 ma high level input voltage v ih 2.2 v cc + 0.5 v 1 low level input voltage v il -0.5 0.8 v 1 input leakage i i 0.0v v i v cc -1.0 1.0 a high level output current i oh v cc =4.75v v oh =4v -1.0 ma low level output current i ol v cc =4.75v v ol =0.5v 12 ma ac electrical characteristics (t a = 25c; v cc = 5v 5%) parameter symbol min typ max units notes period t period 4 (t wi )ns3 input pulse width t wi 40% of tap 5 t plh ns 3 input to tap 1 output delay t plh , t phl table 1 ns 2 tap-to-tap delays t plh table 1 ns 2 output rise or fall time t or , t of 2.0 2.5 ns power-up time t pu 100 ms capacitance (t a = 25c) parameter symbol min typ max units notes input capacitance c in 10 pf
ds1004 5 of 6 notes: 1. all voltages are referenced to ground. 2. v cc =5v and 25 c. delay accuracy on both the rising and falling edges within tolerances given in table 1. 3. pulse width and duty cycle specifications may be exceeded, however, accuracy will be application sensitive with respect to decoupling, layout, etc. test conditions input: ambient temperature: 25 c = 3 c supply voltage (v cc ): 5.0v = 0.1v input pulse: high = 3.0v = 0.1v low = 0.0v = 0.1v source impedance: 50 ohm max. rise and fall time: 3.0 ns max. (measured between 0.6v and 2.4v) pulse width: 500 ns pulse period: 1 s output load capacitance: 15 pf output: each output is loaded with the equivalent of one 74f04 input gate. data is measured at the 1.5v level on the rising and falling edge. note: above conditions are for test only and do not restrict the devices under other data sheet conditions. timing diagram: ds1004 input to outputs
ds1004 6 of 6 terminology period: the time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t wi (pulse width): the elapsed time on the pulse between the 1.5v point on the leading edge and the 1.5v point on the trailing edge or the 1.5v point on the trailing edge and the 1.5v point on the leading edge. t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse. t fall (input fall time): the elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. t plh (time delay, rising): the elapsed time between the 1.5v point on the leading edge of the input pulse and the 1.5v point on the leading edge of the output pulse. t phl (time delay, falling): the elapsed time between the 1.5v point on the falling edge of the input pulse and the 1.5v point on the falling edge of the output pulse.
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